Integrated circuits (ICs) such as digital signal processors (DSPs) include on-chip memory for storage of information. The on-chip memory typically comprises, for example, an array of memory cells connected by word lines in one direction and bit lines in another direction. The memory cells are routinely tested to ensure that the memory is properly readable or writable. Testing may be carried out by writing test patterns into particular memory locations and reading the test patterns to verify that both the written and read-out test patterns are consistent. Those memory locations that produce inconsistent results may be repaired through the use of redundancy schemes, if available.
Built-in self-testing (BIST) circuits may be embedded into the IC to improve the speed and versatility of testing without external hardware. The BIST circuit addresses, writes the test pattern and reads one memory location at a time. However, as the size of the memory increases; especially in multi-bank memory architectures, the number of memory locations to be tested will also increase. This requires more time to test the memory. The longer test times translate into higher manufacturing costs.
As evidenced from the above discussion, it is desirable to provide an improved testing circuit that increases the efficiency of testing.